1. Field of the Invention
The present invention relates to a semiconductor non-volatile memory device and, more particularly, to a technique for preventing the occurrence of a glitch of level "1".fwdarw.level "0".fwdarw.level "1" in a read data output during a transition from a non-selected state to a selected state in a memory device.
2. Description of the Related Art
A conventional Read Only Memory (ROM) such as a ROM using an n-channel Metal Oxide Semiconductor Field Effect Transistor (MOS FET) is arranged in the following manner, as is well known. That is, as for rows, a ROM comprises a row decoder for decoding a row address, a plurality of row lines connected to each of the outputs of the row decoder and a plurality of non-volatile memory cells whose gates are connected to the row lines. Regarding columns, the ROM comprises a column decoder for decoding a column address, a plurality of column lines connected to each of the outputs of the column decoder and the plurality of non-volatile memory cells whose drains and sources are respectively connected to the column lines and a signal ground. Note that binary data can be stored by charging a floating gate or changing the shape of the n-channel MOS FET pattern. In addition, the ROM includes a sense amplifier for detecting and amplifying a small voltage indicating the storage data from the non-volatile memory cell and a buffer amplifier for current-amplifying the output from the sense amplifier. In the sense amplifier or the buffer amplifier, data read out from the memory cell is usually inverted.
In the conventional ROM, row lines are normally made of polysilicon, a polycide or the like, and column lines are normally made of Al. Therefore, it takes time from when a row selection signal is generated at an output of a row decoder to when the output signal is transmitted to a memory cell connected to a row line end. This is because the signal is delayed by resistance and capacitance components of the polysilicon or polycide of the signal line. By this signal delay, a column line connected to the drain of a memory cell connected near the row line end is electrically floated, and a glitch (such as a noise of 10 nS to 20 nS) of level "1".fwdarw.level "0".fwdarw.level "1" may occur at a buffer output.
A cause of the glitch will be described with reference to FIGS. 1 and 2. FIG. 1 shows voltages at both ends of a row line (Vwl1, Vwl1'), a chip selection signal (CE) and an output of a selected memory cell (Vbl). Referring to FIG. 1, reference symbols Vwl1 and Vwl1' denote voltage levels on the row decoder side and the cell side connected to an end of the row line selected before selection of the chip; and Vwl2 and Vwl2', voltage levels on a row decoder side and a cell side connected to an end of a row line selected after selection of the chip, respectively. Reference symbol Vbl indicated by a broken line denotes a voltage level of the same column line selected before/after selection of the chip. FIG. 2 shows an output of a ROM chip in the operation in FIG. 1.
In this case, when the ROM chip is not selected, it is assumed that the row and column decoders select a memory cell which is connected to an end of a row line and set in an OFF state (that is, an output of the cell is set at high level when the cell is selected). Furthermore, it is assumed that a period of non-selection of the ROM chip is longer than that of a memory cycle. When the period of non-selection of the ROM chip becomes longer than that of the memory cycle, a potential of a column line is decreased to a ground potential by a junction leakage current of each cell connected to the column line. It is assumed that when this ROM chip is selected by a computer system, a memory cell is set in an ON state (that is, an output of the cell is set at low level when the cell is selected) and connected to the same column line as before it is selected.
When a chip selection signal is set at a low level (A in FIG. 1) and the chip is selected, a potential Vbl of the column line is immediately output from this chip (F in FIG. 2). That is, the low-level potential of the column line is inverted by the amplifier, and a high-level potential is generated at the output of the chip. A row selection signal is transmitted to the gate of the target memory cell with a delay due to the above-described reason (Vwl1, Vwl1', Vwl2, and Vwl2' in FIG. 1). During this delay period, the output of the memory cell selected in advance is set in a floating state, and a current controlled by the chip selection signal is supplied from the power source to the column line connected to the cell. Therefore, the potential of the column line is increased (B in FIG. 1) over a threshold value of the sense amplifier (C in FIG. 1), and an inverted low-level potential is generated at the chip output (G in FIG. 2). Before long, the row selection signal reaches the gate of the memory cell located at the end of the memory cell array. Since the target memory cell is set in an ON state according to the above assumption, the column line is set at low level (D in FIG. 1). Therefore, an inverted high-level potential is generated at the chip output (H in FIG. 2). Thus, a glitch of level "1".fwdarw.level "0".fwdarw.level " 1" occurs at the chip output (i.e., a buffer amplifier OB output).
Upon generation of such a glitch, a variation in power source voltage (self noise) caused by a change in output current of the buffer amplifier OB is larger than that caused by a change in normal read data output such as level "1".fwdarw.level "0" or level "0".fwdarw.level "1". This is because power source noise (i.e., a variation in power source voltage) is induced by the rapid change in output current such as a glitch. This variation in power source voltage causes degradation of the operation margin of an address input buffer or an error in its operation. Furthermore, the operation error of the address input buffer causes, in turn, a glitch in the output. This may cause oscillation of the memory. The same problem is encountered in other types of ROMs.